The present application describes systems and techniques relating to etching vias in integrated circuit devices, for example, a method of plasma etch for etch stop-less integration.
A conventional via etch process typically has two operations. A bulk of the dielectric material is first removed with a high etch rate. Then, the remaining dielectric material is removed with higher selectivity etching of the ILD (Interlayer dielectric) when compared to the underlying etch stop layer. In an effort to improve device performance, lower dielectric constant ILD material has been explored to replace a more conventional Oxide-based ILD.
Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features and advantages may be apparent from the description and drawings, and from the claims.